Field of the Invention
Technology described herein relates to directional etching of native oxides. Specifically, technology described herein relates to pretreatment of an oxide surface to selectively etch the oxide surfaces.
Description of the Related Art
With the increase in transistor density and subsequent decrease in the cross-sectional dimensions of device nodes, which can be less than 22 nm, pre-clean of native oxides is of particular importance. Pre-clean can include pre-contact clean or pre-silicide clean which requires removal of oxides from the bottom of vias or trenches of narrowing cross-sectional dimensions. As critical dimension of semiconductor devices decreases, distances between neighboring features formed on a semiconductor substrate are also shortened. Thus, it is important to control etching between vias and trenches during precleaning to prevent damaging nearby features.
Current precleaning techniques generally includes a conformal etch of the substrate to remove the native oxides, such as SiO2, prior to deposition of silicides or other contacts. However, a standard conformal etch can lead to excessive cross-sectional enlargement of vias and trenches thus creating possible leakage and ultimate device failure. Other precleaning techniques such as sputter etching remove native oxides from trench or contact bottom surfaces. However, the sputtering process can also lead to redeposition of field oxides at the via or trench opening. The redeposited oxides create an overhang at vias and trenches openings leading to poor subsequent contact fill.
Thus, methods are needed to preferentially etch from the bottom surfaces of features to prevent damage to features during precleaning.